Fujitsu Home Security System MB91401 User Manual

FUJITSU SEMICONDUCTOR

DATA SHEET

Prelminary

2004.11.12

32-Bit Proprietary Microcontroller

LSI Network Security System

MB91401

■ DESCRIPTION

The MB91401 is a network security LSI incorporating a Fujitsu’s 32-bit, FR-family RISC microcontroller with 10/

100Base-T MAC Controller, encryption function and authentication function. The LSI contains an encryption

authentication hardware accelerator that boosts the LSI’s performance for encryption and authentication commu-

nication (IKE/IPsec/SSL) to be demanded further.

The MAC controller has a packet filtering function that reduces the load on the CPU for an increasing amount of

packet processing. In addition, the board has the External interface for high-speed data communication with

various external hosts, USB ports as general-purpose interfaces, and various card interfaces.

■ FEATURES

• Encryption and authentication processing by hardware accelerator function

The LSI performs processing five times faster than by the conventional combination of encryption/authentication

hardware macros and software or about 400 times faster than by software only. In addition, CPU processing load

factor to be involved in the encryption and the authentication processing can be decreased to 1/5 or less.

Also, the LSI uses the embedded accelerator to execute that public-key encryption algorithm about 100 times

faster than by software processing, which generally puts an extremely heavy load microcontrollers.

(Continued)

■ PACKAGE

244-pin plastic FBGA

(BGA-240P-M01)

Prelminary

2004.11.12

MB91401

(Continued)

• CARD Interface (CompactFlash)

The CompactFlash interface is a memory and I/O mode correspondence. It corresponds to the I/O of data such

as not only the memory card but also the communication cards.

• I²C Interface

• Master/slave sending and receiving

• For standard mode (100 Kbps Max)

Prelminary

2004.11.12

MB91401

■ PIN ASSIGNMENT

INDEX

10 11 12 13 14 15 16 17 18 19

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

73 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 54

74 137 192 191 190 189 188 187 186 185 184 183 182 181 180 179 120 53

75 138 193 240 239 238 237 236 235 234 233 232 231 230 229 178 119 52

76 139 194

77 140 195

78 141 196

79 142 197

80 143 198

228 177 118 51

227 176 117 50

226 175 116 49

225 174 115 48

224 173 114 47

223 172 113 46

222 171 112 45

221 170 111 44

220 169 110 43

219 168 109 42

218 167 108 41

(TOP-VIEW)

(SUB240W)

10 81 144 199

11 82 145 200

12 83 146 201

13 84 147 202

14 85 148 203

15 86 149 204

16 87 150 205 206 207 208 209 210 211 212 213 214 215 216 217 166 107 40

17 88 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 106 39

18 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 38

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

: signal (204 lines)

: PLLVDD (1 line) 199

: PLLVSS (1 line) 197

: VDDI (12 lines) 195, 200, 203, 207, 211, 215, 1219, 223

227, 231, 235, 239

: VDDE (9 lines) 83, 196, 202, 208, 214, 220, 226, 232, 238

: VSS (16lins)

1, 19, 37, 55, 193, 198, 201, 205, 209

213, 217, 225, 229, 233, 237

Prelminary

2004.11.12

MB91401

■ PIN NUMBER TABLE

Pin Number

Pin name

VSS

Pin Number

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Pin Number

Pin name

UDP

Pin name

EXD11

EXD14

CFCD2X

UCLKSEL

CFWAITX

N.C.

Pin name

SDA

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

CFD15

ICLK

CFWEX

CFCE1X

CFIORDX

CFA1

CFA5

CFA8

CFD0

CFD3

CFD7

CFD10

CFD13

CFD14

ICS2

USBINS

UDM

ICS0

CFRESET

CFREGX

CFA0

CFA3

CFA7

CFA10

CFD2

CFD5

CFD9

VSS

TDI

UCLK48

TMS

CFOEX

CFCE2X

CFIOWRX

CFA2

CFA6

CFA9

CFD1

CFD4

CFD8

CFD11

CFD12

ICD0

XINI

PLLBYPAS

OSCEB

TEST0

OSCEA

TEST2

SCK0

SIN0

ICD2

ICS1

VDDI

INT5

BREAKI

CLKSEL

TRST

MDI0

VDDE

PLLVSS

VSS

ICD1

PLLVDD

VDDI

MDI2

ICD3

PLLSET0

TEST1

VDDE

TEST3

SIN1

TDO

VSS

A10

MDI1

VDDE

VDDI

A13

VPD

A16

PLLSET1

OSCC

TCK

INITXI

VSS

MCLKO

A21

SOUT0

INT6

NMIX

VDDI

RDX

PLLS

WRX2

CSX0

N.C.

SCK1

SOUT1

INT7

VDDE

VSS

A11

VDDI

A14

A12

A17

A15

VSS

A19

A18

VDDE

VDDI

D12

A22

A20

D15

WRX3

WRX1

CSX1

N.C.

A23

VSS

RDY

VSS

D17

WRX0

CSX6

N.C.

D26

D18

VDDI

D20

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

VDDE

VSS

D23

N.C.

D27

MDCLK

VDDI

TXEN

TXD0

RXD0

TXCLK

RXD2

RXCLK

EXIS16

EXCSX

EXD0/GPIO0

EXD4/GPIO4

EXD7/GPIO7

EXD10

VSS

D10

D13

D11

MDIO

VSS

D16

D14

D19

D22

VDDE

VDDI

D21

D25

D24

D29

EXD3/GPIO3

VSS

D28

D31

D30

TXD2

TXD3

RXDV

COL

CFVS1X

VDDI

TXD1

RXD1

RXER

RXD3

RXCRS

EXA

VDDE

VSS

DREQRX

DREQTX

EXWRX

EXD2/GPIO2

EXD6/GPIO6

EXD9

EXD15

CFVCC3EX

VDDI

EXD12

EXD13

CFCD1X

SCL

CFA4

VSS

EXRDX

EXD1/GPIO1

EXD5/GPIO5

EXD8

VDDE

VDDI

CFRDY

CFD6

Prelminary

2004.11.12

MB91401

■ PIN DESCRIPTION

[SYSTEM]

[ETHERNET MAC CONTROLLER]

XINI

INITXI

TXCLK

TXD3 to TXD0

TXEN

NMIX

INT7 to INT5

MDI2 to MDI0

[OSCILLATOR]

RXCLK

RXER

RXD3 to RXD0

RXDV

OSCEA

OSCC

OSCEB

RXCRS

COL

MDCLK

MDIO

MB91401

[PLL CONTROL]

PLLS

PLLSET1, PLLSET0

PLLBYPAS

CLKSEL

[ICE]

[EXTERNAL IF]

EXCSX

EXA

EXD15 to EXD0/GPIO7 to GPIO0 16

Signal line

196 pin

39 pin

BREAKI

ICS2 to ICS0

ICLK

EXRDX

EXWRX

DREQRX

DREQTX

EXIS16

Power Supply/

GND

ICD3 to ICD0

[JTAG]

[USB IF]

TCK

TRST

USBINS

UCLK48

UCLKSEL

UDP

TMS

N.C.

5 pin

TDI

TDO

[TEST]

UDM

[CARD IF]

VPD

TEST3 to TEST0

[UART]

CFD15 to CFD0

CFA10 to CFA0

CFCE2X, CFCE1X

CFREGX

CFCD2X, CFCD1X

CFVS1X

SIN1, SIN0

BGA-240P-M01

SOUT1, SOUT0

SCK1, SCK0

[MEMORY IF]

CFRDY (CFIREQ)

CFWAITX

A23 to A0 24

D31 to D0 32

RDX

WRX3 to WRX0

CSX0, CSX1, CSX6

RDY

CFVCC3EX

CFRESET

CFOEX

CFWEX

CFIORDX

CFIOWRX

MCLKO

[I²C IF]

SDA

SCL

Prelminary

2004.11.12

MB91401

SYSTEM (9 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Clock input pin

Input pin of clock generated in clock generator. 10 MHz to

50 MHz frequency can be input.

XINI

Reset input pin

This pin inputs a signal to initialize the LSI.

Nega-

tive

When turning on the power supply, apply “0” to the pin until

the clock signal input to the CLKIN pin becomes stable.

All built-in registers and external pins are initialized, and the

built-in PLL is stopped when “0” is asserted to INITXI.

INITXI

NMIX

204

206

Nega-

tive

NMI input pin

Non-Maskable Interrupt signal

External interrupt input pins

INT7

INT6

INT5

150

These pins input an external interrupt request signal.

For external interrupt detection, set the ENIR, EIRR and

ELVR registers of the FR core.

MDI2

MDI1

MDI0

142

Mode pins

These pins determine the operation mode of the LSI.

Always set this bit to “001”.

OSCILLATOR (3 pin)

Pin name Pin no.

Polarity

Circuit

I/O

Function/application

Crystal oscillation input pin

Input pin of crystal oscillation cell.

OSCEA

145

Crystal oscillation control input pin

Oscillation control pin of crystal oscillation cell.

“0” : Oscillation

Nega-

tive

OSCC

“1” : Oscillation stop

Crystal oscillation output pin

Output pin of crystal oscillation cell.

OSCEB

OUT

PLL CONTROL (5 pin)

Pin name Pin no.

Polarity

Circuit

I/O

Function/application

PLL/through mode (reset) switching input pin

“0” : PLL through mode (oscillation stop)

“1” : PLL oscillation mode

PLLS

147

144

Input clock division ratio select input pin

“0” : Input clock direct

“1” : Input clock divided by 2

PLLSET1

PLLSET0

PLLBYPAS

CLKSEL

Division ratio select input to PLL FB pin

“0” : Two dividing frequency is input to the terminal FB.

“1” : Four dividing frequency is input to the terminal FB.

PLL bypass select input pin

“0” : PLL used

“1” : PLL unused

Input clock switching input pin

“0” : XINI (External clock)

“1” : Built-in OSC generating clock

Prelminary

2004.11.12

MB91401

ICE (9 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Emulator break request pin

BREAKI

This pin inputs the emulator break request when an ICE is

connected.

ICS2

ICS1

ICS0

Emulator chip status pins

These pins output the emulator status when an ICE is

connected.

OUT

I/O

Emulator clock pin

This pin serves as the emulator clock pin when an ICE is

connected.

ICLK

ICD3

ICD2

ICD1

ICD0

140

194

139

138

Emulator data pins

These pins serve as the emulator data bus when an ICE is

connected.

I/O

JTAG (5 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

JTAG test clock pin

TCK

146

Note : Please input “1” when unused.

JTAG test reset pin

TRST

TMS

Note : Please input “0” when unused.

TAP controller mode select pin

Note : Please input “1” when unused.

JTAG test data input pin

JTAG test serial data input pin.

TDI

Note : Please input “1” when unused.

JTAG test data output pin

JTAG test serial data output pin

TDO

141

OUT

TEST (5 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Mode pin

Input “0” to this pin.

VPD

143

TEST3

TEST2

TEST1

TEST0

Test pin

Input “0000” to this pin.

Note : Don’t set other than above description.

Prelminary

2004.11.12

MB91401

UART (6 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Serial data input pins

SIN1

SIN0

Serial data input pin of UART built-in FR core.

SOUT1

SOUT0

149

Serial data output pins

Serial data output pin of UART built-in FR core.

OUT

I/O

SCK1

SCK0

148

Serial clock I/O pins

Serial clock input/output pin of UART built-in FR core.

MEMORY IF (66 pin)

Pin name Pin no.

A23

Polarity

Circuit

I/O

Function/application

156

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

155

154

153

152

Address output pins

24 bits address signal pin.

OUT

151

212

210

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

D31

169

110

168

109

218

167

108

166

107

106

105

165

104

164

103

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Data input/output pins

32 bits data input/output signal pin.

I/O

216

163

102

162

101

100

CSX6

CSX1

CSX0

159

Chip select output pins

3-bit chip select signal pin.

Output the “L” level when accessing to external memory.

Nega-

tive

OUT

Read strobe output pin

Read strobing signal pin.

Output the “L” level when read accessing.

Nega-

tive

RDX

WRX3

WRX2

WRX1

WRX0

Write strobing output pins

Write strobing signal pin.

Output the “L” level when write accessing.

Nega-

tive

OUT

158

Memory clock output pin

Clock for peripheral resources pin.

MCLKO

RDY

OUT

External RDY input pin

When the external bus is not completed, the bus cycle can

be extended by inputting “0”.

Posi-

tive

157

Prelminary

2004.11.12

MB91401

ETHERNET MAC CONTROLLER (17 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Clock input for reception pin

RXCLK

MII sync signal during reception. The frequency is 2.5 MHz

at 10 Mbps and 25 MHz at 100 Mbps.

Receive error input pin

It is recognized that there is an error in the reception packet

when “1” is input from the PHY device at receiving.

Posi-

tive

RXER

RXDV

RXCRS

113

172

115

Posi-

tive

Receive data valid input pin

It is recognized that receive data is effective.

Career sense input pin

The state that the reception or the transmission is done is

recognized.

Posi-

tive

RXD3

RXD2

RXD1

RXD0

114

112

Receive data input pins

4-bit data input from PHY device.

Collision detection input pin

Posi-

tive

When TXEN signal is active and “1”, the collision is

recognized. The collision is not recognized without these

conditions.

COL

173

Clock input for transfer pin

TXCLK

TXEN

It becomes synchronous of MII when transmitting. The

frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps.

Transfer enable output pin

It is shown that effective data is on the TXD bus. It is output

synchronizing with TXCLK.

Posi-

tive

OUT

TXD3

TXD2

TXD1

TXD0

171

170

111

Transfer data output pins

4-bit data bus sent to the PHY device. It is output

synchronizing with TXCLK.

OUT

SMI clock output pin

MDCLK

MDIO

222

224

OUT

I/O

SMI IF clock pin

Connect to SMI clock input pin of PHY device.

SMI data input/output pin

Connect to SMI data of PHY device.

Prelminary

2004.11.12

MB91401

EXTERNAL IF (23 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

External chip select input pin

Nega-

tive

EXCSX

Chip select input pin from external host.

External address input pin

Address input pin from external host.

“0” : Register select

EXA

116

“1” : FIFO data select

EXD15

EXD14

EXD13

EXD12

EXD11

EXD10

EXD9

180

122

121

External data input/output pins

The I/O terminal of data bus bit of bit15 to bit8 with an

external host.

I/O

179

120

EXD8

EXD7/GPIO7

EXD6/GPIO6

EXD5/GPIO5

EXD4/GPIO4

EXD3/GPIO3

EXD2/GPIO2

EXD1/GPIO1

EXD0/GPIO0

178

119

228

177

118

External data/GPIO input/output pins

The I/O terminal of data bus bit of bit7 to bit0 with an

external host.

Note : When EXIS16 “0” input, it becomes the I/O terminal

of GPIO7 to GPIO0.

I/O

Nega-

tive

External read strobing input pin

Read strove input pin from external host

EXRDX

EXWRX

117

176

Nega-

tive

External write strobing input pin

Write strove input pin from external host

External data bus width select input pin

Bit width select pin of EXD

“0” : 8 bit

EXIS16

(Note : EXD15 to EXD8 are enabled.)

“1” : 16 bit

Nega-

tive

External reception data request output pin

Recordable data to reception FIFO is shown.

DREQRX

DREQTX

174

175

OUT

External transfer data request output pin

It is shown that there are data in transmission register and

transmission FIFO.

Nega-

tive

Prelminary

2004.11.12

MB91401

USB IF (5 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

USB data D + (differential) pin

I/O signal pin on the plus side of the USB data.

Use the LSI with 25 Ω to 30 Ω (27 Ω recommended)

external series load resistors, 1.5 kΩ pull-up resistors and

about 100 kΩ resistors. Input “0” when the USB macro is

unused.

UDP

I/O

USB data D − (differential) pin

I/O signal pin on the minus side of the USB data.

Use the LSI with 25 Ω to 30 Ω (27 Ω recommended)

external series load resistors, 1.5 kΩ pull-up resistors and

about 100 kΩ resistors. Input “0” when the USB macro is

unused.

UDM

183

182

I/O

USB insert input pin

USB socket input detection pin. Be sure to input “0” when

not using USB macro.

USBINS

UCLK48

48 MHz input (external clock input) pin

This pin inputs an external 48-MHz clock signal.

The USB macro operates based on this clock. Input the

clock with high accuracy (as not only LSI but also a device)

more than 2500 ppm. Input “0” when the USB macro is un-

used.

USB clock select pin

Clock select pin using for USB macro

“0” : Using internal clock

“1” : Using UCLK48

UCLKSEL

124

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MB91401

CARD IF (41 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

CFD15

CFD14

CFD13

CFD12

CFD11

CFD10

CFD9

CFD8

CFD7

CFD6

CFD5

CFD4

CFD3

CFD2

CFD0

137

136

192

135

240

191

134

190

133

CF data input/output pins

I/O data/status/command signal pin to CompactFlash card

side

I/O

CFA10

CFA9

CFA8

CFA7

CFA6

CFA5

CFA4

CFA3

CFA2

CFA1

CFA0

189

132

188

131

236

187

130

CF address 10 to 0 output pins

Address output CFA10 to CFA0 pins to CompactFlash card

side

OUT

186

CF card enable output pin

Byte access output pin to CompactFlash card side

Note : Supported for access to CFD7 to CFD0.

When “L” level is output, odd number byte access of the

word is shown.

Nega-

tive

CFCE2X

128

OUT

CF card enable output pin

Byte access output pin to CompactFlash card side

Note : Supported for access to CFD7 to CFD0.

When “L” level is output at word access, even number byte

access of the word is shown.

Nega-

tive

CFCE1X

When the byte is accessed, the even number byte and odd

number byte access become possible because CFA0 and

CFCE2X are combined and used by it.

CF Attribute/Common switching output pin

Attribute/Common switching output pin to CompactFlash

card side

“H” : Common Memory select

“L” : Attribute Memory select

Nega-

tive

CFREGX

CFCD2X

185

123

OUT

Card connection detect input pin : CFCD2X

Nega-

tive

Checking connection pin of the socket and CompactFlash

card. It is shown that the CompactFlash card was connected

when this signal and CFCD1X are both input by “0”.

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Card connection detect input pin : CFCD1X

Nega-

tive

Checking connection pin of the socket and CompactFlash

card. It is shown that the CompactFlash card was connected

when this signal and CFCD2X are both input by “0”.

CFCD1X

CFVS1X

CF side GND input pin

GND level detection pin from CompactFlash side.

The “0” input to the pin assumes that the CompactFlash

card can operate at 3.3 V, setting the CFVCC3EX pin to the

“L” level.

Nega-

tive

230

CF ready input pin : memory card

Ready input pin from CompactFlash memory card side

“1” : Ready

“0” : Busy

(CF interrupt : I/O card)

Interrupt request pin of CompactFlash I/O card. It is shown

the interrupt request was done from the I/O card when input

to this signal by “0”.

Posi-

tive

(Nega-

tive)

CFRDY

(CFIREQ)

Cycle wait input pin during CF execution

Cycle wait input pin from CompactFlash card side

“0” : It is shown that there is a wait demand at the cycle

under execution.

“1” : It is shown that there is no wait demand at the cycle

under execution.

Nega-

tive

CFWAITX

125

234

CF3.3 V power enable output pin

Outputs “L” level when the CompactFlash card is operable

at 3.3 V.

The output signal enables 3.3-volt power supply to the

CompactFlash card. The pin outputs “L” level only when the

CFVS1X pin detects “0”; otherwise, the pin outputs “H”.

Nega-

tive

CFVCC3EX

OUT

CF reset output pin

Reset output pin to CompactFlash card side.

CompactFlash is reset at “H” output.

Posi-

tive

CFRESET

CFOEX

184

127

OUT

CF read strobe output pin

Read strove output pin to CompactFlash card (memory

mode and Attribute memory area)

Nega-

tive

CF register write output pin

Write clock output pin to CompactFlash card (register write

and Card Configuration Register area).

The register write is executed at the rising edge from “L” to

“H”.

Nega-

tive

CFWEX

OUT

Nega-

tive

CFIO read strobing output pin

Read strove output pin to CompactFlash card (I/O mode)

CFIORDX

CFIOWRX

OUT

Nega-

tive

CFIO write strobing output pin

Write strove output pin to CompactFlash card (I/O mode)

129

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MB91401

I²C IF (2 pin)

Polarity

Circuit

Pin name

SDA

SCL

Pin no.

I/O

Function/application

Serial data line input/output pin

I²C bus data I/O pin

181

I/O

Serial clock line input/output pin

I²C bus clock I/O pin

I/O

Power Supply/GND (39 pin)

Polarity

Circuit

Pin name

Pin no.

I/O

Function/application

Power

supply

APLL dedicated power supply pin

This pin is for 1.8 V power supply pin.

PLLVDD

199

V-E

PLLVSS

VDDE

197

GND

V-S APLL dedicated GND Pin

196

202

208

214

220

226

232

238

Power

supply

V-E 3.3 V power supply pin

195

200

203

207

211

215

219

223

227

231

235

239

Power

supply

VDDI

V-E 1.8 V power supply pin

193

198

201

205

209

213

217

221

225

229

233

237

VSS

GND

V-S GND Pin

Prelminary

2004.11.12

MB91401

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

Digital output

• With pull/down

• CMOS level output

• CMOS level input

• Value of pull-down resistance =

approx. 33 kΩ (Typ)

Digital input

Digital output]

Digital output

• CMOS level output

• CMOS level input

Digital input

D⁺input

D⁻input

D+

D−

Differential input

Full D⁺output

Full D⁻output

USB I/O

Low D⁺output

Low D⁻output

Direction

Speed

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Type

Circuit

Remarks

CMOS level input

Digital input

• With pull-up

• CMOS level input

• Value of pull-up resistance =

approx. 33 kΩ (Typ)

Digital input

Digital output

CMOS level output

Oscillation output

Control

Oscillation circuit

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2004.11.12

MB91401

■ HANDLING DEVICES

Preventing Latch-up

When a voltage that is higher than V^DDEand a voltage that is lower than VSS are impressed to the input terminal

and the output terminal in CMOS IC or the voltage that exceeds ratings between VDDE to VSS is impressed, the

latch-up phenomenon might be caused. If latch-up occurs, the supply current increases rapidly, sometimes

resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum

rating during device operation.

Separation of power supply pattern

Analog PLL (APLL at the following) is installed in this LSI. The power supply for VCO and for digital is separated

in LSI so that the oscillation characteristic of APLL may receive the influence of power supply variation.

Therefore, the power supply is recommended to be separated also on the mounting base.

• Separation of power supply pattern (recommended)

Take measures to reduce impedance, for example, by using as wide a power pattern as possible.

The recommendation example is shown as follows.

• For two power supplies (for digital and for VCO)

It is advisable to provide a digital power-supply (a) and VCO power-supply (b) and connect them to the LSI’s

equivalents, respectively.

Figure For 2-power supply (for digital and for VCO)

VDD (for digital)

LSI

PLLVDD (for VCO)

APLL

Logic part

Power

supply

(a)

Power

supply

(b)

PLLVSS

VSS

• For the common power supply

To share a single power-supply for digital and VCO uses, it is advisable to separate the output into the digital

and VCO wiring patternsand connect them to the LSI.

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2004.11.12

MB91401

Figure When you share the power supply for digital and for VCO

VDD (for digital)

LSI

PLLVDD (for VCO)

APLL

Logic part

Power

supply

(a)

PLLVSS

VSS

Treatment of the unused pins

Leaving unused input pins open results in a malfunction, so process the pull-up or pull-down.

Treatment of OPEN pins

Be sure to use open pins in open state.

Treatment of output pins

A large current may flow to an output pin left connected to the power-supply, another output pin, or to a high

capacitance load. Leaving the output pin that way for an extended period of time degrades the device. Use

meticulous care in using the device not to exceed the absolute maximum rating.

About Mode (MDI2 to MDI0, VPD) pin and Test (TEST3 to TEST0) pin

Connect these pins directly to VDDE or VSS. To prevent the device from entering test mode accidentally due to

noise, minimize the lengths of the patterns between individual mode pins and VDDE or VSS on the PC board

as possible and connect them with as low an impedance as possible.

About power supply pins

In products with multiple VDDE, VDDI or VSS pins, the pins of the same potential are internally connected in

the device to avoid abnormal operations including latch-up. However you must connect the pins to external power

supply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation strobe

signals caused by the rise in the ground level, and to conform to the total output current rating.

The power pins should be connected to VDDE, VDDI and VSS of this device at the lowest possible impedance

from the current supply source.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VDDE and VSS,

and between VDDI and VSS near this device.

Crystal Oscillator Circuit

Noise near the OSCEA terminal may cause the MB91401 to malfunction.

Design the circuit board so that OSCEA terminal, OSCEB terminal and the crystal oscillator, and the bypass

capacitor to ground are located as close to the device as possible.

It is strongly recommended to design the PC board artwork with the OSCEA terminal and OSCEB terminal

surrounded by ground plane because stable operation can be expected with such a layout.

Prelminary

2004.11.12

MB91401

■ CONNECTED SPECIFICATION OF MB91401 AND ICE

Recommended type and circuit configuration of the emulator interface connector mounting on the user system,

attention when designing and wiring regulation are shown.

When the flat cable is used, the combination of the connectors with housing should be selected.

Recommended connector type

Attached cable

FPC cable

Part number

Remarks

FH10A-30S-1SH (Maker : Hirose Electric Co., Ltd.) With latch

• Circuit composition

Please put the dumping resistance 15 Ω in the series in the ICLK terminal signal because of the stability of

operation when connecting it with ICE. Resistance must be mounted near the terminal ICLK of this LSI when

you design the printed wiring board.

Emulator interface connector

MB2198-0 and MB2197-01 side

MCU for evaluation

MB91401

VCC

UVCC

FUSE

15 Ω

ICLK

ICS2 to ICS0

ICD3 to ICD0

BREAKI

RST

BREAKI

INITXI

10 kΩ

xRSTIN

(Open)

Reset output

circuit

GND

VSS

*1 : Use the line (inter connect) to flow the rating current or more.

*2 : The change circuit might become necessary, and refer to “Precaution when designing”.

*3 : Mount resistance near the terminal ICLK of MB91401.

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2004.11.12

MB91401

• Precaution when designing

When evaluation MCU on the user system is operated in the state that the emulator is not connected, should

be treated as follow each input terminal of evaluation MCU connected with the emulator interface on the user

system.

Therefore, note that the switch circuit etc, might become necessary in the user system when you design.

The terminal processing in each emulator interface is shown as follows.

Pin treatment of emulator interface (DSU-3)

Evaluation MCU terminal name

Pin treatment

To be connected the RST terminal with the reset output circuit in the

user system.

RST

Others

To open.

Emulator interface wiring regulations

Signal line name

Wiring regulations

ICLK

• The total wiring length of each signal (From evaluation MCU pin to the

emulator interface connector pin) is made within 50 mm.

• The difference of the total wiring length of each signal makes within 2 cm

and the total wiring length of ICLK is the shortest.

ICS2 to ICS0

ICD3 to ICD0

BREAKI

• Wire the pattern with capacity more than the ratings current.

• Each power supply and GND may cause a short-circuit or reverse connec-

tion in between by a wrong connection of a probe. Insert a protection circuit

such as a fuse into each power supply pattern to safeguard it.

UV^CC

GND

• Connect directly with a power supply system pattern such as grandopran.

• Reference document

Please match and refer to the following manual for the connection with ICE.

• DSU-FR Emulator MB2198-01 Hardware Manual

• FR20/30 series MB2197-01 Hardware Manual

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2004.11.12

MB91401

JTAG

The JTAG function is installed in this LSI.

Note that the terminal INITXI should be input in "L" when using JTAG.

Notes when quartz vibrator is mounted

The crystal oscillation circuit built into this LSI operates by the following compositions.

MB91401

OSC

OSCEB

OSCC

OSCEA

Installation

when over tone

oscillates

Quartz

vibrator

• Pin description

Pin name

OSCC

Function

Oscillation control terminal of crystal oscillation cell (OSC)

Input terminal of crystal oscillation cell (OSC)

OSCEA

OSCEB

Output terminal of crystal oscillation cell (OSC)

When OSCCL is input, the OSCEA and OSCEB oscillate at the natural frequency of the crystal oscillator and

propagated into the LSI.

• Circuit constant on external substrate

Circuit constants

Description

External load capacity

C1, C2, C3

Inductance

Dumping resistance (addition if necessary)

Prelminary

2004.11.12

MB91401

• Reference Value

Oscillation frequency

C1, C2

None

to 30 MHz

5 pF to 33 pF

5 pF to 15 pF

None

20 MHz to 50 MHz

10 nF approx.

1 µH approx.

It is necessary to add C3/L depending on a basic wave and the over tone characteristic of the oscillator of the

20 MHz to 30 MHz belt.

Note : These reference values are standards. The constant changes according to the characteristic of the quartz

vibrator used. Therefore, we will recommend the initial evaluation that uses the evaluation sample to the

decision of the circuit constant. Please contact FUJITSU representatives about the evaluation sample.

• Notes when encryption/authentication accelarator is used

When using the encryption/authentication installed in this LSI, it is necessary to the following notes.

32-bit data bus

The encryption/authentication accelerator fetches data from the area storing data to be subject to encryption/

authentication and encrypts or authenticates the data without CPU intervention. In the encryption processing,

write is done in the area where it wants to store the data after the encryption is processed.

MB91401

32bit

Data Bus

encryption/

authentication

RAM

accelerator

At the storage destination of

encryption/authentication

processing data

Holding request withdrawal demand function OFF

When accessing to the storage destination of encryption/authentication processing data, the encryption/authen-

tication accelerator should hold an internal bus of this LSI.

Therefore, when the encryption/authentication accelerator are used, it should be set that the holding request

withdrawal doesn’t demand.

Please set the HRCL register that sets the interrupt level that becomes the standard of the holding request

withdrawal demand generation to "10000" in the FR core.

For NMIs, the hold request cancel request occurs regardless of the HRCL register setting. When the encryption/

authentication accelerator is used, therefore, NMI input may cause encryption/authentication to fail to result

correctly. In that case, the correspondence said that it will execute the encryption/authentication processing

under execution again is necessary.

Prelminary

2004.11.12

MB91401

• Notes as device

Treatment of Unused Input Pins

It causes the malfunction that the unused input terminal is made open, and do the processing such as 1 stack

or 0 stacks.

About Mode pins (MDI2 to MDI0)

Connect these pins with the input buffer by 1 to 1 to prevent the malfunction by the noise, and connect directly

to VDD or VSS outside of ASIC.

Operation at start-up

Specify set initialization reset (INIT) with the terminal INITXI when you turn on the power supply.

Moreover, connect "L" level input to the terminal INITXI until the input clock is steady.

About watch dog timer

The watchdog timer function of this macro monitors a program to check whether it delays a reset within a certain

period of time. If the program runs out of control and fails to delay the reset, the watchdog timer function resets

the CPU.

Therefore, it keeps operating until reset is specified when the watchdog timer function is made effective once.

Exceptionally, the reset postponement is automatically done under the condition that the program execution of

CPU stops. Refer to the paragraph of the function explanation of the watchdog timer for the condition of applying

to this exception.

There is a possibility that watchdog reset is not generated when entering the above-mentioned state by the

reckless driving of the system. In that case, please specify reset (INIT) from external INITX terminal.

Restrictions

• Clock control block

• Secure the clock stability waiting time at "L" input to INITXI.

• When entering the standby mode, use the following sequences after using the synchronous standby mode

(TBCR:set at the bit8 SYNCS bit of timebase counter control register).

(LDI

#value_of_standby, R0) ; Value_of standby is write data to STCR.

(LDI

#_STCR, R12)

R0, @R12

; _STCR is address (481H) of STCR.

; Write to standby control register (STCR).

; STCR read for synchronous standby

; Dummy re-read of STCR

STB

LDUB

NOP

@R12, R0

In addition, set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt

handler triggers the microcontroller to return from the standby mode.

• Please do not do the following when the monitor debugger is used.

• Please do not set the break point to the above-mentioned instruction row.

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2004.11.12

MB91401

CPU

• The instruction fetch is not done from D-bus, and does not set the code area on D-bus RAM.

• Set neither stack area nor the vector table on the instruction RAM.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event

or emulator menu:

(1) The D0 and D1 flags are updated in advance.

(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.

(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as in (1) .

• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.

(1) The PS register is updated in advance.

(2) Executing of EIT processing routine (user interrupt • NMI)

(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as in (1) .

• Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt

handler to break or the PS flag to update its display setting when the debugger is being used. As the micro-

controller is designed to carry out reprocessing correctly upon returning from such an EIT event in either case,

it performs operations before and after the EIT as specified.

1. When (a) user interrupt and NMI are accepted or (b) step is executed or (c) break is done by the data

event or the menu of the emulator in the instruction immediately before the instruction of DIV0U/DIV0S,

the following operation might be done.

(1) The D0 and D1 flags are updated in advance.

(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.

(1) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as in (3) .

2. When ORCCR, STILM, MOV Ri, and PS each instruction is executed to permit interrupt with the user

interrupt and the NMI factor generated, the following operation is done.

(1) The PS register is updated in advance.

(2) The EIT processing routine (user interrupt, NMI or emulator) is executed.

(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to

the same value as in (1).

• Do not access the data to the cache memory at the control register of the instruction cash and RAM mode

immediately before the instruction of RETI.

• If one of the instructions listed below is executed, the SSP or USP* value is not used as the R15 value and,

as a result, an incorrect value is written to memory.

• Only ten following kinds of instructions that specify R15 as Ri correspond.

AND

R15, @Rj ANDH R15, @Rj ANDB

R15, @Rj

R15, @Rj ORH R15, @Rj ORB

R15, @Rj

EOR

R15, @Rj EORH R15, @Rj EORB R15, @Rj

XCHB @Rj, R15

* : As for R15, there are no realities. When R15 is accessed from the program, SSP or USP is accessed by the

state of "S" flag of the PS register. Please specify general registers other than R15 when ten above-mentioned

instructions are described by the assembler.

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2004.11.12

MB91401

• External bus interface

• When the bus width of the area set up as little endian is 32-bit, confine to word (32-bit) access when accessing

the relevant area.

• When enabling prefetch to the area set to the Little endian, give the access to the corresponding area as word

(32 bits) access limitation. In the byte and the half word access, it is not possible to access it correctly.

• DMA

• Do not transfer DMA to instruction RAM.

• Bit Search Module

• BSD0, BSD1, and the BDSC register are only the word accesses.

Prelminary

2004.11.12

MB91401

■ NOTES OF DEBUG

Step execution of RETI instruction

In an environment where interrupts frequently occur during single-step execution, only the relevant interrupt

processingroutinesareexecutedrepeatedlyduringsingle-stepexecutionoftheRETIinstruction. Thiswillprevent

the main routine and low-interrupt-level programs from being executed.

Do not execute step of RETI instruction for escape.

When the relevant interrupt routine no longer requires being debugged, disable the relevant interrupt and perform

debugging.

Operand break

Do not set the access which is used for area, including the address of system stack pointer, to the target of data

event break.

Interrupt handler to NMI request (tool)

To prevent the malfunction because of the noise problem of DSU pin when ICE is unconnected, the following

programs are added to the interrupt handler by the cause flag, which is only set by the break request from ICE.

ICE can be used even if this program is added.

Location to added

The following interrupt handler

Interrupt resource

Interrupt number

Offset

: NMI request (tool)

: 13 (decimal), 0D (hexadecimal)

: 3C8^H

TBR is default address. : 000FFFC8H

Additional program

STM (R0, R1)

LDI #B00^H, R0 ; B00H is address of the break resource register.

LDI #0, R1

STB R1, @R0 ; Clear the break resource register.

LDM (R0, R1)

RETI

Trace mode

If the trace mode is set to "Full trace mode" during debug (in full trace mode, built-in FIFO is used as output

buffer, the trace memory of the main body of ICE is used, and the trace data lost is not occurred), the electric

current is increased and D-busDMA access may be lost.

Also, the trace data lost may be occurred.

To take the measures, do not set full trace mode.

Simultaneous generation of a software break and a user interrupt/NMI

When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as

follows.

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

When these problems are occurred, not only the software break, the hardware break should also be used. Do

not set the break to the corresponding location when using monitor debugger.

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2004.11.12

MB91401

■ BLOCK DIAGRAM

OSC

FR core

Crystal Unit

CLKIN

CLK

Cont

D-RAM (8 KB)

I-Cach (4 KB)

DMAC

USB CLK (48 MHz)

PLL

Serial IF

(2ch)

UART

INT

Timer

DSU

DSU IF

PHY

INT/NMI

Authentication macro

LAN controller

10/100 Ethernet

MAC Controller

IPsec Accelerator

(IKE Accelerator)

DES/3DES

HMAC-MD5/SHA1

L3/L4 Filtering

USB Function

Rev2.0FS

USB IF

CARD IF

CompactFlash IF

I²C Bus

External IF

GPIO

Ext. IF/

PORT

I²C IF

MEMORY IF

MB91401

FLASH

SRAM

FR core : CPU, U-Timer, UART, Timer, Interrupt controller, DMAC, Bit search, External interrupt, Memory_IF,

Data-RAM, Cache, Bus controller

Peripheral resources : LAN, External_IF, GPIO, Card, Encryption/Authentication, I²C, USB (Peripheral resource

is connected to bus of bus controller. )

Prelminary

2004.11.12

MB91401

■ MEMORY SPACE

• Memory space

The FR family has 4 GByte of logical addresses (2³²address) which can be linearly accessed by the CPU.

Direct Addressing Areas

The following address space areas are used as I/O areas.

These areas are called direct addressing areas, in which the address of an operand can be specified directly

during an instruction.

The direct addressing area varies as shown below depending on the size of access data:

→ byte data access

→ half word data access

→ word data access

: 0-0FF^H

: 0-1FFH

: 0-3FFH

• Memory Map

The memory space of the macro consists of the following areas.

0000 0000H

0000 0400H

0001 0000H

0002 0000H

0003 F800H

Direct Addressing Areas

Refer to I/O Map

I/O

I-bus RAM 4 KB

(and its mirror)

Access disallowed area

D-bus RAM 8 KByte

0004 0000H

External area

FFFF FFFFH

Prelminary

2004.11.12

MB91401

■ GENERAL PURPOSE REGISTERS

32 bits

Initial Value:

XXXX XXXXH

R12

R13

R14

R15

XXXX XXXXH

0000 0000H

Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory

access pointers for CPU operations.

Of these 16 registers, the registers listed below are intended for special applications, for which some instructions

are enhanced.

R13: Virtual accumulator

R14: frame pointer

R15:Stack pointer

The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000^H(SSP value).

Prelminary

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MB91401

■ MODE SETTINGS

The FR family uses the mode pins (MDI2 to MDI0) and the mode register (MODR) to set the operation mode.

• Mode Pins

Three mode pins MDI[2], MDI[1], and MDI[0] are used to specify a mode vector fetch or test mode.

Mode pins

Reset vector

access area

Mode name

Remarks

MDI2 to MDI0

0 0 0

Reserved

0 0 1

external ROM mode vector

User circuit test

Reserved

External

Bus width is set by the mode data.

FR stops (with clock signal supplied).

0 1 0

0 1 1

1 0 0

Reserved

1 0 1

Reserved

1 1 0

Reserved

1 1 1

Reserved

Setting MDI2 to MDI0 to "010", USRTEST is set to "1" and the device operates in the user circuit test mode. The

FR71 core is suspended in the user circuit test mode while SYSCLK and MCLKO are operating. The reserved

modes include the FR71 core test mode. In this case, the signal at the FRTEST pin becomes "1" and enters the

FR71 core test mode. If the FRTEST pin = "1", that circuit configuration is required which allows the separately

defined pins of the FR71 core to be controlled and monitored from the outside of the chip.

• Mode Register (MODR)

The data written to the mode register (MODR) by hardware using a mode vector fetch is called mode data.

When this register is set by hardware, the CPU operates in the operation mode corresponding to the register

setting.

The mode register is set only by an INIT-level reset cause. The user program cannot access this register.

However, as an exception, when the macro shifts to emulation mode by INTE instruction, or shifts to emulation

mode by a break at a debug using ICE, this register is mapped at 0000_07FD^H. Select this function when using

ICE, perform the mode data setting before the program loading by writing a appropriate value to this register.

Note : No data is existed in the address (0000_07FFH ) in the mode register of the FR family.

• Register

Initial Value

MODR

WTH1 WTH0

XXXXXXXXB

Operation mode setting bits

[bit7 to bit2] Reserved bit

Be sure to set this bit to “000000”. Setting them to any other value may result in an unpredictable operation.

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MB91401

[bit1, bit0] WTH1, WTH0 (Bus width setting bits)

These bits specify the bus width. The value of the bits is set in the DBW1 and DBW0 bits in ACR0 (CSO area).

Set these bits to a value other than “11”.

WTH1

WTH0

Function

Remarks

External bus mode

8-bit bus width

16-bit bus width

32-bit bus width

Setting disabled

• Operation mode

In the operation mode, there are a bus mode and an access mode.

Bus mode

Access mode

32-bit bus width

16-bit bus width

8-bit bus width

External ROM

bus

Bus mode

In bus mode, the operations of internal ROM and the external access functions are controlled according to the

mode setting pins (MD2 to MD0) and the values of mode data.

Although the FR71 architecture supports this bus mode, this macro cannot use the single-chip or internal ROM/

external bus mode but can use the external ROM/external bus mode only.

Access mode

Access mode indicates the mode that controls the external data bus width, and is specified by the WTH1/WTH0

bits, and the DBW1/DBW0 bits within ACR0 to ACR7 (Area Configuration Registers).

Bus mode

The FR family has three bus modes described below. Please refer to “■ MEMORY SPACE” for details.

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MB91401

■ I/O MAP

This shows the location of the various peripheral resource registers in the memory space.

[How to read the table]

Address

Block

+ 0

+ 1

+ 2

+ 3

0000_0000^H

Reserved

Ext Int

0000_003CH

EIRR [R/W]

00000000

ENIR [R/W]

00000000

ELVR [R/W]

00000000 00000000

0000_0040^H

Read/Write attribute

Initial value after a reset

at address 4n + 2)

Left most register address (When accessing it by word, the register of

column 1 is positioned on the MSB side of data.)

Note : Initial values of register bits are represented as follows :

“1” : Initial Value “1”

“0” : Initial Value “0”

“X” : Initial Value “X”

“-” : Access prohibited in reserved area.

Address

Block

+ 0

+ 1

+ 2

+ 3

0000_0000^H

Reserved

0000_003CH

EIRR [R/W]

00000000

ENIR [R/W]

00000000

ELVR [R/W]

00000000 00000000

0000_0040H

0000_0044^H

0000_0048^H

0000_004CH

0000_0050^H

0000_0054^H

0000_0058^H

0000_005CH

Ext Int

DICR [R/W]

-------0

HRCL [R/W]

0-11111

DLYI/I-unit

TMRLR0 [W]

XXXXXXXX XXXXXXXX

TMR0 [R]

XXXXXXXX XXXXXXXX

Reload Timer 0

Reload Timer 1

TMCSR0 [R/W]

----0000 00000000

TMRLR1 [W]

XXXXXXXX XXXXXXXX

TMR1 [R]

XXXXXXXX XXXXXXXX

TMCSR1 [R/W]

----0000 00000000

TMRLR2 [W]

XXXXXXXX XXXXXXXX

TMR2 [R]

XXXXXXXX XXXXXXXX

Reload Timer 2

(Continued)

TMCSR2 [R/W]

----0000 00000000

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MB91401

Address

Block

+ 0

+ 1

+ 2

+ 3

SSR0 [R/W]

00001-00

SIDR0 [R/W]

XXXXXXXX

SCR0 [R/W]

00000100

SMR0 [R/W]

00--0-0-

0000_0060^H

0000_0064^H

0000_0068H

0000_0048^H

UART0

U-TIMER0

UART1

UTIM0 [R] (UTIMR0 [W])

00000000 00000000

DRCL0 [W]

--------

UTIMC0 [R/W]

0--00001

SSR1 [R/W]

00001-00

SIDR1 [R/W]

XXXXXXXX

SCR1 [R/W]

00000100

SMR1 [R/W]

00--0-0-

UTIM1 [R] (UTIMR1 [W])

00000000 00000000

DRCL1 [W]

--------

UTIMC1 [R/W]

0--00001

U-TIMER1

0000_0070^H

Reserved

0000_01FCH

DMACA0 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

0000_0200^H

0000_0204^H

0000_0208H

0000_020CH

0000_0210^H

0000_0214H

0000_0218^H

0000_021CH

0000_0220^H

0000_0224H

DMACB0 [R/W]

00000000 00000000 00000000 00000000

DMACA1 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

DMACB1 [R/W]

00000000 00000000 00000000 00000000

DMACA2 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

DMAC

DMACB2 [R/W]

00000000 00000000 00000000 00000000

DMACA3 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

DMACB3 [R/W]

00000000 00000000 00000000 00000000

DMACA4 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

0000_0228^H

0000_023CH

Reserved

DMAC

DMACR [R/W]

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

0000_0240^H

0000_0244H

Reserved

0000_0300H

ISIZE [R/W]

------10

Instruction

Cache

0000_0304H

(Continued)

Prelminary

2004.11.12

MB91401

Address

Block

+ 0

+ 1

+ 2

+ 3

0000_0308^H

Reserved

0000_03E0H

ICHRC [R/W]

0-000000

Instruction

Cache

0000_03E4^H

0000_03E8H

Reserved

0000_03ECH

BSD0 [W]

0000_03F0^H

0000_03F4^H

0000_03F8H

0000_03FC^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search

Module

BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0000_0400H

Reserved

0000_043CH

ICR00[R/W]

---11111

ICR01[R/W]

---11111

ICR02[R/W]

---11111

ICR03[R/W]

---11111

0000_0440^H

0000_0444^H

0000_0448H

0000_044CH

0000_0450H

0000_0454^H

0000_0458H

0000_045C^H

0000_0460^H

0000_0464H

0000_0468H

ICR04[R/W]

---11111

ICR05[R/W]

---11111

ICR06[R/W]

---11111

ICR07[R/W]

---11111

ICR08[R/W]

---11111

ICR09[R/W]

---11111

ICR10[R/W]

---11111

ICR11[R/W]

---11111

ICR12[R/W]

---11111

ICR13[R/W]

---11111

ICR14[R/W]

---11111

ICR15[R/W]

---11111

ICR16[R/W]

---11111

ICR17[R/W]

---11111

ICR18[R/W]

---11111

ICR19[R/W]

---11111

ICR20[R/W]

---11111

ICR21[R/W]

---11111

ICR22[R/W]

---11111

ICR23[R/W]

---11111

Interrupt Control

Unit

ICR24[R/W]

---11111

ICR25[R/W]

---11111

ICR26[R/W]

---11111

ICR27[R/W]

---11111

ICR28[R/W]

---11111

ICR29[R/W]

---11111

ICR30[R/W]

---11111

ICR31[R/W]

---11111

ICR32[R/W]

---11111

ICR33[R/W]

---11111

ICR34[R/W]

---11111

ICR35[R/W]

---11111

ICR36[R/W]

---11111

ICR37[R/W]

---11111

ICR38[R/W]

---11111

ICR39[R/W]

---11111

ICR40[R/W]

---11111

ICR41[R/W]

---11111

ICR42[R/W]

---11111

ICR43[R/W]

---11111

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Address

Block

+ 0

+ 1

+ 2

+ 3

ICR44[R/W]

---11111

ICR45[R/W]

---11111

ICR46[R/W]

---11111

ICR47[R/W]

---11111

Interrupt Control

Unit

0000_046C^H

0000_0470^H

Reserved

0000_047CH

RSRR [R/W]

10000000*²

STCR [R/W]

00110011*²

TBCR [R/W]

00XXXX00*¹

CTBR [R/W]

XXXXXXXX

0000_0480H

0000_0484^H

Clock Control

Unit

WPR [W]

XXXXXXXX

DIVR0 [R/W]

00000011*¹

DIVR1 [R/W]

00000000

Access disallowed

0000_0488H

Reserved

0000_063FH

ASR0 [R/W]

00000000 00000000

ACR0 [R/W]

0000_0640^H

0000_0644^H

0000_0648H

0000_064CH

0000_0650^H

0000_0654H

0000_0658^H

0000_065CH

0000_0660^H

0000_0664H

0000_0668^H

0000_066C^H

1111**00 00000000*³

ASR1 [R/W]

XXXXXXXX XXXXXXXX

ACR1 [R/W]

XXXXXXXX XXXXXXXX

ASR2 [R/W]

XXXXXXXX XXXXXXXX

ACR2 [R/W]

XXXXXXXX XXXXXXXX

ASR3 [R/W]

XXXXXXXX XXXXXXXX

ACR3 [R/W]

XXXXXXXX XXXXXXXX

ASR4 [R/W]

XXXXXXXX XXXXXXXX

ACR4 [R/W]

XXXXXXXX XXXXXXXX

ASR5 [R/W]

XXXXXXXX XXXXXXXX

ACR5 [R/W]

XXXXXXXX XXXXXXXX

ASR6 [R/W]

XXXXXXXX XXXXXXXX

ACR6 [R/W]

XXXXXXXX XXXXXXXX

ASR7 [R/W]

XXXXXXXX XXXXXXXX

ACR7 [R/W]

XXXXXXXX XXXXXXXX

Memory IF

AWR0 [R/W]

01111111 11111111

AWR1 [R/W]

XXXXXXXX XXXXXXXX

AWR2 [R/W]

XXXXXXXX XXXXXXXX

AWR3 [R/W]

XXXXXXXX XXXXXXXX

AWR4 [R/W]

XXXXXXXX XXXXXXXX

AWR5 [R/W]

XXXXXXXX XXXXXXXX

AWR6 [R/W]

XXXXXXXX XXXXXXXX

AWR7 [R/W]

XXXXXXXX XXXXXXXX

MCRA MCRB

XXXXXXXX XXXXXXXX

0000_0670H

0000_0674H

0000_0678H

IOWR0 [R/W]

XXXXXXXX

IOWR1 [R/W]

XXXXXXXX

IOWR2 [R/W]

XXXXXXXX

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Address

Block

+ 0

+ 1

+ 2

+ 3

0000_067C^H

CSER [R/W]

00000001

CHER [R/W]

XXXXXXX1

TCR [R/W]

00000000*¹

0000_0680H

0000_0684H

Memory IF

RCR

00XXXXXX

0000_0688^H

Reserved

0000_0FFCH

*1 : An initial value is a different register at the reset level. The display is the one at the INIT level.

*2 : An initial value is a different register at the reset level. The display is due to the INIT level by INITX.

*3 : An initial value is set by the WTH bit of the mode vector.

Address

Block

+ 0

+ 1

+ 2

+ 3

DMASA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0000_1000^H

0000_1004^H

0000_1008H

0000_100C^H

0000_1010^H

0000_1014H

0000_1018^H

0000_101CH

0000_1020H

0000_1024^H

DMADA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

DMADA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0000_1028H

Reserved

0000_FFFCH

Prelminary

2004.11.12

MB91401

Address

Block

+ 0

+ 1

+ 2

+ 3

BSR[R]

00000000

BCR[R/W]

00000000

CCR[R/W]

10000000

ADR[R/W]

1XXXXXXX

010F_0000^H

010F_0004H

DAR[R/W]

XXXXXXXX

BC2R[R/W]

00XX0000

I²C

010F_0008^H

(Reserved)

010F_FFFFH

Address

Block

+ 0

+ 1

+ 2

+ 3

DLCR0*

0X000000

DLCR1[R, W]

00000000

DLCR2*

00000000

DLCR3[R/W]

00000000

0110_0000^H

0110_0004^H

0110_0008^H

0110_000CH

0110_0008^H

0110_000C^H

0110_0008^H

0110_000CH

0110_0010H

LAN controller

DLCR4*

00000010

DLCR5*

01000001

DLCR6*

10000000

DLCR7*

00000000

DLCR8[R/W]

00000000

DLCR9[R/W]

00000000

DLCR10[R/W]

00000000

DLCR11[R/W]

00000000

Bank 0

Bank 1

DLCR12[R/W]

00000000

DLCR13[R/W]

00000000

MAR8[R/W]

00000000

MAR9[R/W]

00000000

MAR10[R/W]

00000000

MAR11[R/W]

00000000

MAR12[R/W]

00000000

MAR13[R/W]

00000000

MAR14[R/W]

00000000

MAR15[R/W]

00000000

BMPR10*

00000000

BMPR11*

00000111

BMPR12*

00000000

BMPR14*

00000000

Bank 2

BMPR8

00000000-00000000

FILTER_CMD

[R/W]

00000000-00000000

0110_0014H

0110_0018^H

0110_001CH

0110_0020^H

0110_0024H

[R/W]

XXXXXXXX

FILTER_STATUS

[R]

XXXXXXXX

FILTER_DATA

[R/W]

XXXXXXXX

FL_CONTROL

[R/W]

XXXXXXXX

FL_SUBNET

[R/W]

XXXXXXXX

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Address

Block

+ 0

SMI_CMD[R/W]

00000000-00000000

SMI_CMD_ST

[R/W]

00XXXXXX

SMI_DATA [R/W]

+ 1

+ 2

+ 3

0110_0028^H

0110_002C^H

SIM IF

0110_0030^H

0110_0034^H

00000000-00000000

SMI_POLLINTVL [R/W]

00000000-00000000

SMI_PHY_ADD

0110_0038^H

[R/W]

00000XXX

SMI_CONTROL

[R/W]

0110_003C^H

0110_0040^H

0110_0044^H

111XXXXX

SMI_STATUS[R]

XXXXXXXX

SIM IF

SMI_INTENABLE

[R/W]

0XXXXXXX

SMI_MDCDIV

[R/W]

0110_0048^H

01011XXX

* : The attribute is different according to the bit.

Prelminary

2004.11.12

MB91401

Address

Block

+ 0

+ 1

EXIFRXDR [R]

+ 2

+ 3

0114_0000^H

0114_0004^H

0114_0008H

0114_000C^H

0114_0010^H

0114_0014H

0114_0018^H

0114_001CH

0114_0020H

00000000-00000000 00000000-00000000

EXIFTXDR [W]

00000000-00000000 00000000-00000000

EXIFRXR[R]

00000000-00000000

EXIFTXR[W]

00000000-00000000

External IF

EXIFCR[W]

00000000-0XXXXXXX

EXIFSR[R]

00000000-00XXXXXX

EXIFRXSR [R]

00000000-00000000 00000000-00000000

EXIFTXSR [R]

00000000-00000000 00000000-00000000

PIOCR[R/W]

00000000

GPIO

PIODR[R/W]

Connecting

destination

0114_0024^H

Address

Block

+ 0

+ 1

+ 2

+ 3

IR[R/W]

00000000

DR[R/W]

10000011

(Reserved)

RR[R/W]

00000000

0500_03E0^H

0501_0000H

0501_07FFH

AMR

CompactFLASH

(Attribute Memory Area : window 0)

0501_1000H

0501_17FFH

CMR

(Common Memory Area : window 1)

Prelminary

2004.11.12

MB91401

Address

Block

+ 0

+ 1

+ 2

+ 3

FIFO0out[R]

XXXXXXXX-XXXXXXXX

FIFO0in[W]

XXXXXXXX-XXXXXXXX

0540_0000^H

0540_0004^H

0540_0008H

FIFO1[R]

XXXXXXXX-XXXXXXXX

FIFO2[W]

XXXXXXXX-XXXXXXXX

FIFO3[W]

XXXXXXXX-XXXXXXXX

0540_000C^H

(Reserved)

0540_001FH

CONT1[R/W]

XXXXX0XX-XXX00000

0540_0020^H

0540_0024H

0540_0028^H

0540_002CH

0540_0030H

0540_0034^H

0540_0038H

CONT2[R/W]

XXXXXXXX_XXX00000

CONT3[R/W]

XXXXXXXX_XXX00000

CONT4[R/W]

XXXXXXXX_XXX00000

CONT5[R/W]

XXXXXXXX_XXXX00XX

USB

CONT6[R/W]

XXXXXXXX_XXXX00XX

CONT7[R/W]

XXXXXXXX_XXX00000

CONT8[R/W]

XXXXXXXX_XXX00000

CONT9[R/W]

XXXXXXXX_0XXX0000

CONT10[R/W]

XXXX0000_X000000X

TTSIZE[R/W]

00010001-00010001

TRSIZE[R/W]

00010001-00010001

0540_003C^H

0540_003FH

(Reserved)

RSIZE0[R]

XXXXXXXX-XXXX0000

0540_0040^H

0540_0044^H

RSIZE1[R]

XXXXXXXX-X0000000

0540_0048H

0540_005FH

ST1[R/W]

XXXXXX00-00000000

USB

0540_0060^H

0540_0064^H

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Address

Block

+ 0

+ 1

+ 2

+ 3

ST2[R]

XXXXXXXX-X0000000

ST3[R/W]

XXXXXXXX-XXX00000

0540_0068^H

0540_006C^H

ST4[R]

XXXXX000-00000000

ST5[R/W]

XXXX0XXX-XX000000

0540_0070H

0540_007BH

(Reserved)

USB

RESET[R/W]

XXXXXXXX-XXXXXX00

0540_007C^H

0540_0080H

(Reserved)

0540_FFFFH

Address

Block

+ 0

+ 1

+ 2

+ 3

MACRORR[W/R]

00000000-00000001

CARDSR[R/W]

00000000-00000000

0580_0000^H

0580_0004H

0580_0008^H

CARDIMR[R/W]

00000000-00000000

CARDISR[R]

00000000-00000000

Chip Register

USBPLLRP[R/W]

00000000-00000000

Prelminary

2004.11.12

MB91401

■ INTERRUPT VECTOR

Interrupt number

Interrupt

level

Address of TBR

Interrupt source

Offset

Hexa-

Decimal

default

decimal

Reset

3FCH

3F8^H

3F4^H

3F0H

3EC^H

3E8^H

3E4H

3E0^H

3DCH

3D8^H

3D4H

3D0H

3CC^H

3C8H

3C4H

3C0H

3BCH

3B8^H

3B4H

3B0H

3ACH

3A8H

3A4H

3A0H

39C^H

398H

394H

390^H

38CH

388H

384^H

380H

37CH

378^H

000FFFFCH

000FFFF8H

000FFFF4H

000FFFF0H

000FFFECH

000FFFE8H

000FFFE4H

000FFFE0H

000FFFDCH

000FFFD8H

000FFFD4H

000FFFD0H

000FFFCCH

000FFFC8H

000FFFC4H

000FFFC0H

000FFFBCH

000FFFB8H

000FFFB4H

000FFFB0H

000FFFACH

000FFFA8H

000FFFA4H

000FFFA0H

000FFF9CH

000FFF98H

000FFF94H

000FFF90H

000FFF8CH

000FFF88H

000FFF84H

000FFF80H

000FFF7CH

000FFF78H

Mode vector

System reserved

Coprocessor absent trap

Coprocessor error trap

INTE instruction

Instruction break exception

Operand break trap

Step trace trap

NMI request (tool)

Undefined instruction exception

NMI request

F^Hfixed

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

Ethernet MAC IF

Authentication macro

IPSec Accelerator/Code macro

EX IF/GPIO

USB/I²C/CARD IF

External interrupt 5

External interrupt 6

External interrupt 7

Reload timer 0

Reload timer 1

Reload timer 2

UART0 (Reception completed)

UART1 (Reception completed)

UART0 (RX completed)

UART1 (RX completed)

DMAC0 (end error) Ethernet MAC IF

DMAC1 (end error) External IF

DMAC2 (end error) USB

(Continued)

Prelminary

2004.11.12

MB91401

Interrupt number

Interrupt

level

Address of TBR

Interrupt source

Offset

Hexa-

Decimal

default

decimal

DMAC3 (end, error)

DMAC4 (end, error)

System reserved

U-TIMER0

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

374H

370H

36C^H

368^H

364H

360^H

35C^H

358H

354^H

350H

34C^H

348H

344H

340^H

33CH

338H

334^H

330H

32C^H

328H

324H

320^H

31CH

318H

314H

310^H

30CH

308H

304^H

300H

2FCH

2F8^H

2F4H

2F0H

000FFF74H

000FFF70H

000FFF6CH

000FFF68H

000FFF64H

000FFF60H

000FFF5CH

000FFF58H

000FFF54H

000FFF50H

000FFF4CH

000FFF48H

000FFF44H

000FFF40H

000FFF3CH

000FFF38H

000FFF34H

000FFF30H

000FFF2CH

000FFF28H

000FFF24H

000FFF20H

000FFF1CH

000FFF18H

000FFF14H

000FFF10H

000FFF0CH

000FFF08H

000FFF04H

000FFF00H

000FFEFCH

000FFEF8H

000FFEF4H

000FFEF0H

U-TIMER1

Timebase timer overflow

System reserved

Delay interrupt source bit

System reserved (Used by REALOS*)

System reserved

(Continued)

Prelminary

2004.11.12

MB91401

(Continued)

Interruptnumber

Interrupt

level

Address of TBR

Interrupt source

Offset

Hexa-

Decimal

default

decimal

System reserved

2ECH

2E8^H

2E4^H

2E0H

2DC^H

2D8^H

2D4H

2D0^H

2CCH

2C8^H

2C4H

2C0H

000FFEECH

000FFEE8H

000FFEE4H

000FFEE0H

000FFEDCH

000FFED8H

000FFED4H

000FFED0H

000FFECCH

000FFEC8H

000FFEC4H

000FFEC0H

2BC^H

000FFEBCH

Used by INT instruction

255

000H

000FFC00H

(2) NMI (Non Maskable Interrupt)

NMIs have the highest priority among the interrupt sources handled by this module.

An NMI is always selected whenever other types of interrupt sources occur at the same time.

• If an NMI occurs, the interrupt controller passes the information to the CPU :

Interrupt level : 15 (01111^B)

Interrupt number : 15 (0001111B)

• NMI detection

NMIs are set and detected by the external interrupt/NMI controller. This module only generates an interrupt

level, interrupt number, and MHALTI upon NMI request.

• Suppressing DMA transfer upon NMI request

When an NMI request occurs, the MHALTI bit in the HRCL register is set to "1", suppressing DMA transfer. To

permit DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.

Prelminary

2004.11.12

MB91401

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Remarks

Parameter

Symbol

Unit

Min

Max

I/O

Internal

VDDE

V^DDI

PLLVDD

VSS − 0.3

VSS + 4.0

VSS + 2.5

VSS + 4.0

Power supply

voltage*¹

Analog power supply voltage

Input voltage*¹

VDDE + 0.3

T.B.D

Output voltage*¹

“L” level maximum output current

“L” level average output current

“L” level total maximum output current

“L” level total average output cur rent

“H” level maximum output current

“H” level average output current

“H” level total maximum output current

“H” level total average output cur rent

Power consumption

I^OL

°C

I^OLAV

ΣI^OL

ΣI^OLAV

I^OH

I^OHAV

ΣI^OH

ΣI^OHAV

P^D

Operating temperature

− 10

− 55

Storage temperature

Tstg

150

°C

*1 : This parameter is based on VSS = PLLVSS = 0 V.

*2 : Note that analog power supply voltage and input voltage do not exceed VDDE + 0.3 V at power on.

*3 : The maximum output current is the peak value for a single pin.

*4 : The average output current is the average current for a single pin over a period of 100 ms.

*5 : The total average output current is the average current for all pins over a period of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Notes : • Apply equal potential to all of the VDDE pins.

• Apply equal potential to all of the VDDI pins.

• Fix all of the VSS pins at 0 V.

• Leave N.C. pins open.

Prelminary

2004.11.12

MB91401

2. Recommended Operating Conditions

(VSS = PLLVSS = 0 V)

Value

Typ

3.3

Parameter

Symbol

Unit

Max

Min

3.0

I/O

Internal

V^DDE

V^DDI

3.6

1.95

Power supply voltage

1.65

1.8

Analog power supply voltage

Operating temperature

PLLVDD

VSS + 3.0

− 10

VDDE

70.0

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Prelminary

2004.11.12

MB91401

3. DC Characteristics

• Other than USB

(VSS = PLLVSS = 0 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

“H” level input

voltage

V^IH

V^IL

V^OH

V^OL

I^LI

2.0

VDDE + 0.3

“L” level input

voltage

VSS − 0.3

0.8

“H” level output

voltage

VDDE = 3.0 V,

IOH = 4.0 mA

VDDE − 0.5

“L” level output

voltage

VDDE = 3.0 V,

I^OH= 4.0 mA

0.4

VDDE = 3.6 V,

VSS < VI < VDDE

Input leak current

Pull-up resistance

± 5

µA

TCK/TRST/TMS/

TDI/TDO/

CFCD2X/

CFCD1X/

CFVS1X/CFRDY/

CFWAITX

R^PULU

kΩ

Pull-down

resistance

R^PULDCFRESET

VDDE

VDDI = 1.8 V,

VDDE = 3.3 V,

fc = 50 MHz

T.B.D

Power supply

current

I^CC

VDDI

Without power

supply

Input capacitance

C^IN

Prelminary

2004.11.12

MB91401

• USB

(VSS = PLLVSS = 0 V)

Value

Typ

Symbol

Remarks

Parameter

Conditions

Unit

Min

Max

“H” level output

voltage

V^OH

VOL

I^OH

IOH = − 100 µA

IOL = 100 µA

VDDE − 0.2

VDDE

“L” level output

voltage

0.2

“H” level output

current

VOH = VDDE − 0.4 V

VOL = 0.4 V

− 20

“L” level output

current

I^OL

output short circuit

current

IOS

ILZ

300

mA *1

Input leak current

± 5

µA *2

*1 : <About the output short-circuit current>

Output short-circuit current I^OSis the maximum current that flows when the output pin is connected to VDDE

or VSS (within the maximum rating) . The current is “the short-circuit current per differential output pin.” As the

USB I/O buffer is a differential output, the short-circuit current should be considered for both of the output pins.

Monitor the short-circuit current

“L” level

“H” output

Short-circuited at GND level

Short-circuited at VDDE level

3-State Enable "L"

“H” level

Monitor the short-circuit current

3-State Enable "L"

*2 : <About Measurement of Z leakage current I^LZ>

Input leakage current ILZ is measured with the USB I/O buffer in the high-impedance state when the VDDE

or VSS voltage is applied to the bidirectional pin.

Monitor the leakage current

Z output

0 V, VDD level applied to output pin

3-State Enable "H"

Prelminary

2004.11.12

MB91401

USB Specification Revision 1.1

Parameter

Value

Symbol

Unit

Remarks

Min

Max

Input Levels

High (driven)

V^IH

V^IL

2.0

Low

0.8

2.5

Diffential Input Sensitivity

Differential Common Mode Range

Output Levels

V^DI

VCM

0.2

0.8

High (driven)

V^OH

VOL

0.0

2.8

1.3

0.3

3.6

2.0

Low

Output Signal Crossover Voltage

Terminations

V^CRS

Bus Pull-up Resistor on Upstream Port

R^PU

1.425

3.0

1.575

3.6

kΩ

1.5 kΩ ± 5%

Termination Voltage for Upstream Port

Pull-up

VTERM

*1 : <Input Levels V^IH, VIL>

The switching threshold voltage of the USB I/O buffer’s single-end receiver is set within the range from

VIL (Max) = 0.8 V to VIH (Min) = 2.0 V (TTL input standard) .

For VIH and VIL, the LSI has some hysteresis to reduce noise susceptibility.

*2 : <Input Levels V^DI, VCM>

A differential receiver is used to receive USB differential data signals.

The differential receiver has a differential input sensitivity of 200 mV when the differential data input falls within

the range from 0.8 V to 2.5 V with respect to the local ground reference level.

The above voltage range is referred to as common-mode input voltage range.

1.0

0.2

0.8

2.5

Common mode input voltage (V)

*3 : <Output Levels V^OL, VOH>

The output driving performance levels of the driver are 0.3 V or less (to 3.6-V, 1.5 kΩ load) in the low

state (V^OL) and 2.8 V or more (to ground, 1.5 kΩ load) in the high state (VOH) .

Prelminary

2004.11.12

MB91401

*4 : <Output Levels V^CRS>

The cross voltage of the external differential output signals (D+ and D−) falls within the range from 1.3 V to 2.0 V.

D+

Max 2.0 V

VCRS standard range

Max 1.3 V

D−

*5 : <Terminations V^TERM>

VTERM indicates the pull-up voltage at the upstream port.

Prelminary

2004.11.12

MB91401

4. AC Characteristics

The following measurement conditions depending on the supply voltage apply to the MB91401 unless otherwise

specified.

• AC measurement condition

Input

Output

VCC

VIH

VOH

VIL

VOL

0 V

VIH

VDDE × 0.8

VDDE × 0.2

VOH

VOL

VDDE/2

V^IL

VDDE/2

• Load condition

C = 55 pF

(1) Clock

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Fclkcyc

XINI

External clock

Oscillation

10.0

50.0

MHz

Input clock frequency

OSCEA,

OSCEB

10.0

50.0

Internal operating clock frequency

(FR70E/peripheral module)

Fclkin

Fusop

Fi2op

50.0

48.0

MHz

Internal operating clock frequency

(USBC)

Internal operating clock frequency

(I²C IF)

12.5

50.0

MHz

External memory clock frequency

MCLKO

* : The clock frequency must be set to over 25 MHz for the Ethernet MAC interface to perform 100 Base

communication.

Fclkcyc

XINI

OSCEA/OSCEB

Prelminary

2004.11.12

MB91401

(2) Reset

Value

Symbol

Parameter

Conditions

Unit Remarks

Min

Max

After power At unusing of PLL

supply &

5 tcp

µs

Reset input time

trstl

INITXI

PLLS

At using of PLL 600 + 1

input clock

PLL reset input time tprstl

At using of PLL

stabilization

Note : tcp is internal CPU and clock cycle period for peripheral module.

trstl, tprstl

INITXI

PLLS

Prelminary

2004.11.12

MB91401

(3) Normal memory access

Value

Parameter

Symbol

Typical timing

Unit Remarks

Min

Max

Address delay time

CSX delay time

WRX delay time

Data delay time

RDX delay time

Data setup

tchav

tchcsl

A23 to A0

MCLKO ↑

tcycp / 2 + 7 ns

CSX2 to CSX0

tchcsh CSX2 to CSX0

tchwrl WRX3 to WRX0

tchwrh WRX3 to WRX0

− 1

tchdv

tchrdl

tchrdh

tdsrh

D31 to D0

RDX

tcycp / 2 + 7 ns

− 1

RDX

D31 to D0

Data hold

trhdx

Note : tcycp is external memory clock cycle period.

tcycp

MCLKO

tchav

A23 to A0

tchcsl

tchcsh

CSX2 to CSX0

tchwrl

tchwrh

WRX3 to WRX0

D31 to D0

tchdv

tchrdl

tchrdh

RDX

tdsrh

D31 to D0

trhdx

Prelminary

2004.11.12

MB91401

(4) Ready input

Parameter

Value

Symbol

Typical timing

Unit Remarks

Min

Max

RDY setup

RDY hold

trdys

trdyh

RDY

MCLKO ↑

− 1

MCLKO

RDY

trdys

trdyh

Prelminary

2004.11.12

MB91401

(5) UART

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Serial clock

cycle time

tscyc

tslov

tivsh

tshix

tshsl

tslsh

tslov

tivsh

tshix

SCK1, SCK0

SOUT1, SOUT0

SIN1, SIN0

8 × timcycp

− 80

SCLK ↓ →

SOUT delay time

Internal

shift clock

mode

Valid SIN →

SCLK ↑

100

SCLK ↑ →

valid SIN hold time

SIN1, SIN0

Serial clock

“H” Pulse Width

SCK1, SCK0

SOUT1, SOUT0

SIN1, SIN0

4 × timcycp

Serial clock

“L” Pulse Width

External

shift clock

mode

SCLK ↓ →

SOUT delay time

150

Valid SIN →

SCLK ↑

SCLK ↑ →

valid SIN hold time

SIN1, SIN0

Note : timcycp is operational clock period of peripheral module built-in FR70E core.

Prelminary

2004.11.12

MB91401

• Internal shift clock mode

SCK1, SCK0

tscyc

VOH

VOL

tslov

SOUT1, SOUT0

SIN1, SIN0

tshix

tivsh

• External shift clock mode

tslsh

tshsl

SCK1, SCK0

tslov

SOUT1, SOUT0

SIN1, SIN0

tshix

tivsh

Prelminary

2004.11.12

MB91401

(6) MII interface

Parameter

Value

Symbol

Typical timing

Unit Remarks

Min

Max

TXEN delay time

TXD delay time

RXDV setup time

RXSV Hold Time

RXD setup time

RXD Hold Time

RXERsetup time

RXER Hold Time

tdel_txen

tdel_txd

tsu_rxdv

thd_rxdv

tsu_rxd

TXEN

TXD3 to TXD0

RXDV

TXCLK ↑

RXCLK ↑

RXDV

RXD3 to RXD0

thd_rxdv RXD3 to RXD0

tsu_rxer

thd_rxer

RXER

• Transmission

TXCLK

tdel_txen

TXEN

TXD3 to TXD0

tdel_txd

TXCLK

TXEN

tdel_txen

n−1

TXD3 to TXD0

tdel_txd

Prelminary

2004.11.12

MB91401

• Reception

RXCLK

RXDV

thd_rxdv

tsu_rxdv

thd_rxdv

RXD3 to RXD0

tsu_rxd

RXCLK

RXDV

thd_rxdv

tsu_rxdv

tsu_rxd

n−1

RXD3 to RXD0

thd_rxdv

RXCLK

RXER

tsu_rxer

thd_rxer

tsu_rxer

thd_rxer

Prelminary

2004.11.12

MB91401

(7) MDIO interface

Parameter

Value

Symbol

typical timing

Unit Remarks

Min

Max

MDIO setup time

MDIO Hold Time

MDIO delay time

tsu_mdio

thd_mdio

tdel_mdio

MDIO

MDCLK ↑

MDIO switching time

(IN → OUT)

tdel_turnon

tdel_turnoff

MDIO

MDCLK ↑

MDIO switching time

(OUT → IN)

MDCLK

tsu_mdio

thd_mdio

MDIO (INPUT)

tsu_mdio

thd_mdio

MDCLK

MDIO (OUTPUT)

tdel_mdio

MDCLK

Input Mode

Output Mode

MDIO

(INPUT OUTPUT)

tdel_turnon

MDCLK

Output Mode

Input Mode

MDIO

(OUTPUT INPUT)

tdel_turnoff

Prelminary

2004.11.12

MB91401

(8) External IF

• Read access

Value

Parameter

Symbol

Unit

Remarks

Min

Max

EX Read Cycle time

EXA to Data Valid

texrc

texadv

texcsdv

texdoe

texdhz

EXA, EXCSX

EXA, EXD

6 × tcp

5 × tcp

EXCSX to Data Valid

EXRDX to Data Out Enable

EXRDX “H” to High Z

EXCSX, EXD

EXRDX, EXD

5 × tcp + 8

Note : tcp is internal CPU and operational clock period for peripheral module.

texrc

texadv

EXA

texcsdv

EXCSX

EXWRX

texdoe

EXRDX

EXD15: to EXD0

texdhz

Prelminary

2004.11.12

MB91401

• Write access

Value

Parameter

Symbol

Unit

Remarks

Min

5 × tcp

4 × tcp

Max

EX Write Cycle time

EXA to Data Setup time

EXCSX to Data Setup time

EXWRX “L” Pulse width

EXD Setup time

texwc

texads

texcsds

texwp

texds

EXA, EXCSX

EXA, EXD

EXCSX, EXD

EXRDX, EXD

EXD Hold time

texdh

Note : tcp is internal CPU and operational clock period for peripheral module.

texwc

texads

EXA

texcsds

EXCSX

texwp

EXWRX

texds

tchdv

EXD15 to EXD0

texdhz

EXRDX

Prelminary

2004.11.12

MB91401

(9) USB interface

Parameter

Value

Typ

Symbol

Unit

Remarks

Min

Max

Input clock

RISE Time

Fall Time

tucyc

tutfr

UCLK48

UDP, UDM

48*¹

MHz 2500ppm accuracy*¹

ns *2

tutff

Differential Rise and Fall

Timing Matching

tutfrfm UDP, UDM

tzdrv UDP, UDM

111.11

Ω

Driver Output Resistance

tucyc

UCLK48

UDP

UDM

90%

10%

tutfr

tutff

*1 : The AC characteristics of the USB interface conform to USB Specification Revision 1.1.

*2 : <Driver Characteristics TFR, TFF, TFRFM>

These items specify the differential data signal rise (trise) and fall (tfall) times.

These are defined as the times between 10% to 90% of the output signal voltage.

For the full-speed buffer, trise and tfall are specified such that the tr/tf ratio falls within ± 10% to minimize RFI

radiation.

*3 : <Driver Characteristics ZDRV>

USB full-speed connection is performed via a shielded twisted-pair cable at a characteristic impedance of

90 Ω ± 15%. The USB Standard stipulates that the USB driver’s output impedance must be within the range

of 28 Ω to 44Ω. The USB Standard also stipulates that a discrete serial resistor (R^S) must be added to have

balance while satisfying the above standard.

The output impedance of the USB I/O buffer on this LSI is about 3 Ω to 19 Ω. Serial resistor RS to be added

must be 25 Ω to 30 Ω (27 Ω recommended) .

Capacitor CL of 50 pF must be added as well.

Prelminary

2004.11.12

MB91401

Full-speed Buffer

28 Ω to 44 Ω Equiv. Imped

T×D+

CL = 50 pF

T×D−

CL = 50 pF

3-State

Notes : • Driver output impedance 3 Ω to 19 Ω

• Rs series resistance: 25 Ω to 30 Ω

• Add a series resistor of preferably 27 Ω

Prelminary

2004.11.12

MB91401

(10) I²C interface

• Input timing specification

Value

Parameter

Symbol

Unit

Remarks

Min

250

Max

SDA input setup time

SDA input hold time

SCL cycle time

ts2sdai

th2sdai

tcscli

SDA

SCL

µs

SCL input “H” pulse time

SCL input “L” pulse time

SCL input setup time

SCL input hold time

twhscli

twlscli

ts2scli

th2scli

4.7

* : Initial Value : I²C bus standards.

STOP START

RESTART

ACK

ts2scli

SDA(input)

ts2scli

th2scli

ts2sdai

th2sdai

th2scli

SCL(input)

tcscli

twhscli

twlscli

• Output timing specification

Value

Parameter

Symbol

Unit

Remarks

Min

Max

SCL output cycle time

SCL output “H” Pulse Time

SCL output “L” Pulse Time

SCL output setup time

SCL output hold time

tcsclo

twhsclo

twlsclo

ts2sclo

th2sclo

th2sdao

SCL

SDA

(2 × m) + 2

m + 2

PCLK

m + 2

m × 2

SDA output hold time

* : For value m, refer to Section 7.5.2.3 “Clock Control Register (CCR) in the I²C Interface Specifications.” PCLK

indicates I²C interface operating clock frequency.

STOP

START

RESTART

ACK

SDA (output)

ts2sclo

th2sclo

th2sdao

ts2sclo

th2sclo

SCL (output)

tcsclo

twhsclo

twlsclo

Prelminary

2004.11.12

MB91401

(11) Card IF

• Read access

Value

Parameter

Symbol

Unit Remarks

Min

Max

CFA10 to CFA0,

CFCE2X, CFCE1X

CF Read Cycle time

CFA to Data Valid

CFCEX to Data Valid

tcfrc

tcfadv

tcfcedv

tcfdoe

CFA10 to CFA0,

CFD15 to CFD0

CFCE2X, CFCE1X,

CFD15 to CFD0

CFOEX CFIORDX to Data Out

Enable

CFOEX, CFIORDX,

CFD15 to CFD0

CFOEX, CFIORDX,

CFD15 to CFD0

CFOEX CFIORDX “H” to High Z tcfdhz

tcfrc

tcfadv

CFA10 to CFA0

tcfcedv

CFCE2X, CFCE1X

CFWEX, CFIOWRX

tcfdoe

CFOEX, CFIORDX

CFD15 to CFD0

tcfdhz

Prelminary

2004.11.12

MB91401

• Write access

Value

Parameter

Symbol

Unit Remarks

Min

Max

CFA10 to CFA0,

CFCE2X, CFCE1X

CF Write Cycle time

tcfwc

tcfads

tcfceds

CFA10 to CFA0,

CFD15 to CFD0

CFA to Data Setup time

CFCEX to Data Setup time

CFCE2X, CFCE1X,

CFD15 to CFD0

CFWEX CFIOWRX “L” Pulse

width

tcffwp CFWEX, CFIOWRX

CDWEX, CFIOWRX,

tcfds

CFD Setup time

CFD Hold time

CFD15 to CFD0

CDWEX, CFIOWRX,

tcfdhz

CFD15 to CFD0

tcfwc

tcfads

CFA10 to CFA0

tcfceds

CFCE2X, CFCE1X

tcffwp

tcfds

CFWEX, CFIOWRX

CFD15 to CFD0

tcfdhz

CFOEX, CFIORDX

Prelminary

2004.11.12

MB91401

■ ORDERING INFORMATION

Part number

Package

Remarks

240-pin plastic FBGA

(BGA-240P-M01)

MB91401

Prelminary

2004.11.12

MB91401

■ PACKAGE DIMENSION

240-pin plastic FBGA

(BGA-240P-M01)

Note: The actual shape of coners may differ from the dimension.

240-¯0.30±0.10

(240-¯.012±.004)

0.05(.002)

10.00±0.10(.394±.004)SQ

1.13 ^+0.20

(Mounting height)

Ð0.10

.044 ^+.008

Ð.004

0.50(.020)

TYP

9.00(.354)

REF

0.10(.004)

INDEX

(INDEX AREA)

W V U T R P N M L K J H G F E D C B A

0.25±0.10

(.010±.004)

(Stand off)

1999 FUJITSU LIMITED B240001S-2C-2

Dimensions in mm (inches).

Note : The values in parentheses are reference values.

Prelminary

2004.11.12

MB91401

MEMO

Prelminary

2004.11.12

MB91401

FUJITSU LIMITED

For further information please contact:

Japan

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

FUJITSU LIMITED

Marketing Division

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Electronic Devices

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Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

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Tel: +1-408-737-5600

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

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Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Tel: +65-6281-0770

Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

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Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

2004 FUJITSU LIMITED Printed in Japan

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